Staff Hardware Design Engineer - NoC (Network-on-Chip)

Join a pioneering semiconductor technology company shaping the future of system connectivity and performance.

Our client develops advanced interconnect and system IP solutions used in complex System-on-Chip (SoC) designs across industries such as AI, automotive, high-performance computing, and mobile devices. Their configurable interconnect technology enables efficient communication between compute, memory, and accelerator subsystems in modern chips, helping leading semiconductor companies build scalable and high-performance silicon platforms.

As a Staff Hardware Design Engineer, you will play a key role in the design and development of highly configurable on-chip communication solutions. You will collaborate closely with architecture, design, and verification teams to deliver high-quality hardware IP that integrates seamlessly into advanced SoC environments.

This role offers the opportunity to contribute to cutting‑edge chip architectures and work on technology used by some of the world’s most innovative semiconductor and technology companies.

Key Responsibilities

• Design and implement hardware blocks for configurable IP, including RTL development and performance optimization.
• Contribute to architectural specifications and design decisions for interconnect and NoC components.
• Develop and maintain verification environments to ensure high-quality and reliable designs.
• Collaborate with verification teams to achieve functional coverage and validation targets.
• Work closely with hardware and software teams to support smooth integration within larger SoC platforms.
• Participate in continuous improvement of design methodologies and development processes.
• Engage in technical discussions with application engineering teams and customers when required.
• Document design specifications and track progress throughout the development cycle. Staff Hardware Design Engineer …

Required Experience & Skills

• Master’s degree in Electronic Engineering, Computer Engineering, or a related discipline.
• 5–8 years of experience in SoC, IP, or Network‑on‑Chip (NoC) design.

Strong understanding of coherent and non‑coherent communication protocols such as:

• AMBA / AXI
• ACE
• CXL
• CHI or comparable protocols.
• Solid knowledge of CPU architectures (ARM or RISC‑V) and cache hierarchies.

Hands‑on experience with the full SoC/IP development flow, including:

• Specification and architecture definition.
• Verification.
• Synthesis.
• Timing and power constraints.
• Strong RTL skills using Verilog/SystemVerilog and familiarity with simulation tools such as Cadence, Synopsys, or Mentor.
• Experience with SystemC, C++, Python, or scripting languages is considered a plus.
• Excellent problem‑solving abilities and strong collaboration and communication skills.
• Fluency in English , both written and spoken.

If your experience aligns with the skills and requirements above, we encourage you to apply now or send your CV to