Principal HW Architect

A growing, innovator in the semiconductor system IP domain is searching for a key contributor to define and optimize cache coherency solutions.

You will be a leading figure in developing cutting‑edge cache‑coherent interconnect IP and ensuring seamless integration with other NoC interconnects and system IP, enabling efficient and coherent communication between multiple processor cores, accelerator cores, and functional units.

Key Responsibilities

1. Cache Coherency Architecture
   • Provide expertise and evaluate industry‑standard cache coherency protocols, in addition to proprietary coherency protocol used within the highly configurable NoC IP
   • Develop scalable and robust cache coherency architectures aligned with overall System‑on‑Chip (SoC) designs
   • Analyze customer requirements for cache‑coherent system architectures, including partitioning large designs into chiplets using die‑to‑die and chip‑to‑chip standards such as CHI C2C, UAlink, UCIe, and PCIe
   • Define performance, power, and area (PPA) targets for configurable IP
2. NoC Integration
   • Collaborate with SoC design teams to ensure seamless integration of cache coherency into system architectures
   • Optimize cache coherency architecture and microarchitecture within the NoC to reduce latency and increase bandwidth
3. Performance and Power Optimization
   • Analyze performance bottlenecks and power consumption challenges
   • Propose and implement innovative solutions to improve overall efficiency
   • Work closely with hardware and software teams to verify and optimize cache coherency mechanisms
4. Protocol Verification
   • Support verification teams in defining verification strategies to ensure correctness and robustness of cache coherency protocols and their implementation within the NoC IP
   • Support emulation teams in testing and debugging to validate cache coherency behavior across functional and performance scenarios
5. Cross‑Functional Collaboration
   • Interact with marketing and sales teams to capture customer input and understand market and product requirements
   • Collaborate with hardware design, software development, and system architecture teams to address technical needs and challenges
   • Provide technical expertise and support to Application Engineering teams to assist with customer integration products
6. Industry Research and Innovation
   • Stay up to date with the latest advancements in cache coherency, NoC technologies, and die‑to‑die interfaces
   • Evaluate emerging standards, methodologies, and industry trends, and propose their adoption to enhance IP offerings
7. Documentation and Communication
   • Produce detailed technical documentation, including architecture specifications, design guidelines, and white papers
   • Communicate complex technical concepts clearly to both technical and non‑technical stakeholders

Required Qualifications

• Proven experience as a Cache Coherency Architect, SoC/NoC Architect, or senior design engineer
• In‑depth knowledge of SoC and NoC architectures, cache coherency protocols, and memory hierarchies
• Strong understanding of cache hierarchies and their interaction with NoC interconnects
• + 12 year’s experience in cache coherency verification and validation
• Familiarity with hardware description languages (HDLs) and SoC design tools
• Strong analytical, problem‑solving, and system‑level thinking skills
• Excellent communication and collaboration abilities

Desirable

• Experience designing complex coherent systems
• Strong knowledge of CHI, UCIe, PCIe, UAlink, and related standards
• Prior experience contributing to NoC IP or large‑scale SoC projects

Education

• Bachelor’s, Master’s, or PhD degree in a relevant engineering field, or equivalent professional experience

For further details please reach out to Em Feely -