Mid-Level PCIe/IP Verification Engineer (Hybrid)

A semiconductor technology company is seeking a mid-level Design and Verification Engineer to join the PHY integration team. This full-time position in France involves responsibilities such as Verilog RTL design and ensuring IP integrations, with a requirement for 6+ years of experience and a strong analytical mindset. The role offers a hybrid work environment and a competitive compensation package including salary, bonuses, and employee benefits.

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