Logic Designer Integrator Tester

Overview

Rambus is seeking a full‑time Design Engineer to join our IP / PCIe CXL team in Aix‑en‑Provence, France. The role involves developing features, reference designs, and prototyping on FPGA.

Responsibilities

• Define reference design / example architectures to best demonstrate features of Rambus PCIe / CXL controller IP
• Participate in FPGA prototyping and hardware validation
• Run and improve quality checks (ASIC synthesis, CDC/RDC/Linting, simulation)
• Collaborate with a worldwide team
• Contribute to technical improvements on all aspects of the IP design domain

Qualifications

• RTL coding: Verilog / VHDL
• Master’s degree or PhD in Electrical Engineering, Computer Engineering or equivalent
• Good English communication skills and willingness to work with an international team

Desirable Skills

• Knowledge of ASIC and FPGA design flow and tools (ASIC synthesis, CDC/RDC/Linting, Quartus, Vivado)
• CI experience: Python / Jenkins / GIT

EEO Statement

Rambus is proud to be an Equal Employment Opportunity and affirmative action employer. We do not discriminate based upon race, religion, color, national origin, sex, sexual orientation, gender identity, gender expression, age, veteran status, disability, genetic information or other legally protected characteristics. Rambus provides reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures.