Logic Designer Integrator Tester

Overview\n\n

Rambus, a premier chip and silicon IP provider, is seeking to hire a motivated full-time Design engineer to join our IP / PCIe CXL team in Aix-en-Provence, France. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.\n\n

This full-time position will allow the candidate to develop features and reference designs to show the potential of the IP, to simulate it and to prototype it on cutting edge FPGA.\n\n

Rambus offers a flexible work environment, embracing a hybrid approach. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work.

Responsibilities\n\n

Define reference design / example architectures to best demonstrate features of Rambus PCIe / CXL controller IP\n\n

Participate in FPGA prototyping and hardware validation\n\n

Run and improve quality checks (ASIC synthesis, CDC/RDC/Linting, simulation)\n\n

Collaborate with a worldwide team\n\n

Contribute to technical improvements on all aspects of the IP design domain

Qualifications\n\n

RTL coding : Verilog / VHDL\n\n

Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent.\n\n

Good English skills, communication skills, and willingness to work with an international team. skills, and willingness to work with an international team.\n\n

Additional Desirable skills\n\n

Knowledge of ASIC and FPGA design flow and tools (ASIC Synthesis, CDC / RDC / Linting, Quartus, Vivado)\n\n

CI : Python / Jenkins / GIT

About Rambus\n\n

Rambus is a global company that makes industry-leading memory interface chips and