Junior DFT Engineer - ASIC/FPGA Test & Validation

A technology recruitment company is seeking a Junior DFT Engineer to join their R&D team in France. This role involves developing test strategies for ASIC and FPGA designs. Candidates should have a Master's in Electrical Engineering, along with 2-5 years of relevant experience. Strong debugging skills and familiarity with EDA tools are essential. Salary ranges from €40,000 to €55,000 based on experience.

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