Digital Verification Engineer - UVM / VHDL / Verilog / TCL / Python

Digital Verification Engineer - UVM / VHDL / Verilog / TCL / Python - Expanding Semiconductor company - Growth Opportunities

I'm currently on the lookout for an experienced Digital Verification Engineer.

You will be working for a well funded, rapidly expanding, semiconductor company that has over €40 million of funding to date.

For this role, you will develop and execute comprehensive verification strategies at both subsystem and top‑level, ensuring ASIC functional requirements are fully met, while contributing to the evolution of verification methodologies and flow enhancements. In this role, you will build and maintain robust testbenches and self‑checking test cases, drive RTL and Gate Level Simulation regressions with thorough coverage analysis, and collaborate closely with Analog Design, Software, and Silicon Validation teams to support mixed‑signal simulations, emulation platform activities, and post‑silicon SoC evaluation.

This is a permanent full time role with a preference to being on‑site in either Paris, Caen or Grenoble, however, also open to remote in France on a case‑by‑case basis.

For this Digital Verification Engineer position, I'm interested in speaking to people with the following:

• 3-8+ years experience in digital verification
• Good experience with System Verilog
• Experience with UVM is a bonus
• Knowledge of a digital hardware description languages (VHDL or Verilog) and scripting languages (TCL, Perl, Python)

I welcome your application if you'd like to find out more and if you know someone it would suit, we offer a fantastic referral scheme which I would be happy to discuss.