Design Verification Engineer H/F Arteris

Key Responsibilities

• Define, document, develop, and execute simulation-based verification tests for Arteris’ Register Bank Compiler tool, compatible with RTL simulators (Cadence, Synopsys, Siemens)
• Develop a Python framework for the automatic generation of SystemVerilog and/or UVM test benches
• Maintain and enhance tests within the continuous integration flow, refine metrics, and increase automation
• Contribute to the improvement of processes, methodologies, and performance indicators
• Use modern documentation, specification, and project tracking tools (Confluence, Jira)
• Collaborate with developers to identify EDA‑specific testing requirements
• Participate in code reviews and unit testing with other developers to ensure code quality