Design Verification Engineer — Automation & Test Frameworks

Semiconductor Engineering in Paris is looking for a candidate to define, document, and execute simulation-based verification tests for their Register Bank Compiler tool. The ideal applicant will have skills in Python and experience with EDA tools such as Cadence and Synopsys. Responsibilities include developing a framework for generating System

Verilog test benches, enhancing continuous integration processes, and collaborating with developers on testing requirements. The role offers opportunities for process improvement and automation.

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