Coherence Verification Engineer – RTL, CHI & Cache

TechBiz Global GmbH is seeking a skilled Coherency Verification Engineer in Lyon, France to verify complex digital designs at RTL level. The role involves developing verification environments using SystemVerilog and UVM, along with collaboration across teams to address specifications and requirements.

The ideal candidate will possess a Master or PhD, fluency in English (C1), and over 8 years of industrial experience in verification processes, as well as strong problem-solving skills.