Coherence Verification Engineer – RTL, CHI & Cache

TechBiz Global GmbH is seeking a Coherency Verification Engineer in Toulouse, France. The ideal candidate must verify complex digital designs at RTL level, using SystemVerilog and UVM, with an emphasis on coherent systems.

Applicants should have a Master or PhD and more than 8 years of industrial experience. Strong problem-solving and communication skills are essential, as well as proficiency in scripting languages for automating verification flows.