Verification Engineer - Sr Staff

Founded in 2003, InvenSense Inc., a TDK Group Company, is the world’s leading provider of MEMS sensor platforms. InvenSense’s vision of Sensing Everything targets the consumer electronics and industrial markets with integrated Motion and Sound solutions. Our solutions combine MEMS (micro electrical mechanical systems) sensors, such as accelerometers, gyroscopes, compasses, and microphones with proprietary algorithms and firmware that intelligently process, synthesize, and calibrate the output of sensors, maximizing performance and accuracy. InvenSense’s motion tracking, audio and location platforms, and services can be found in many of the world’s largest and most iconic brands including smartphones, tablets, wearables, drones, gaming devices, internet of things, automotive products, and remote controls for smart TVs.

InvenSense is headquartered in San Jose, CA and has offices in Boston, China, Taiwan, Korea, Japan, France, Canada, Slovakia, and Italy.

We’re looking for top-notch Engineers to join our global team.

If you’re interested in being a part of our journey and helping us grow to become the leading provider of SoC platform solutions, we definitely want to hear from you.

Position Summary

We are looking for a highly experienced Senior Staff ASIC Verification Engineer to lead the verification of complex digital designs. The ideal candidate will have deep expertise in advanced verification methodologies, strong leadership skills, and a proven track record of successfully verifying sophisticated SoCs/ASICs from concept to silicon.

Key Responsibilities

• Lead end-to-end verification of complex digital IP blocks and subsystems
• Define and implement comprehensive verification strategies and test plans
• Develop advanced UVM testbench architectures and reusable verification components
• Drive coverage closure and sign-off quality metrics
• Perform block-level and system-level verification
• Develop and enhance verification methodologies and flows
• Create and maintain advanced verification infrastructure using Python/Perl/TCL scripting
• Build behavioral models and reference models for complex protocols
• Implement coverage-driven and assertion-based verification strategies
• Optimize simulation performance and regression efficiency
• Work closely with design, architecture, system, and physical implementation teams
• Provide technical mentorship to junior and mid-level verification engineers
• Conduct design and testplan reviews
• Lead debug efforts for complex functional and timing issues
• Drive best practices and process improvements across the verification team
• Own verification schedules and deliverables for assigned blocks
• Identify project risks and develop mitigation strategies
• Present verification status and quality metrics to management
• Participate in post-silicon validation and debug

Required Qualifications

Experience

• 10+ years of hands-on ASIC/FPGA verification experience
• 5+ years of experience with UVM methodology
• Proven track record of multiple successful tape-outs
• Experience leading verification projects from specification to silicon

Education

• BS in Electrical Engineering, Computer Engineering, or Computer Science required
• MS or PhD preferred

Technical Skills

Verification Methodologies

• Expert-level proficiency in SystemVerilog and UVM
• Deep understanding of constrained random verification
• Functional coverage and code coverage analysis
• Assertion-based verification (SVA)
• Experience with formal verification tools (bonus)

Tools & Simulators

• Required: Cadence simulation tools (Xcelium/IES/SimVision)
• Highly Preferred: Synopsys VCS and DVE
• Experience with debug tools and waveform viewers
• Familiarity with coverage tools (IMC, URG, or equivalent)

Scripting & Programming

• Strong proficiency in Python and/or Perl
• Experience with TCL scripting
• Shell scripting (bash/csh)
• Familiarity with version control (Git, SOS)

Modeling

• C/C++ or SystemC for reference model development
• Protocol monitors and checkers
• Performance modeling experience (plus)

Technical Knowledge

• Strong understanding of RTL design principles
• Experience with industry-standard protocols (e.g., AMBA AHB/APB,I2C/SPI/I3C,.. etc.)
• Knowledge of low-power verification techniques (UPF)
• Knowledge of Gate Level Simulation verification

Preferred Qualifications

• Experience with Synopsys VCS simulator and associated tools
• Formal verification experience (JasperGold, VC Formal)
• Post-silicon validation and bring-up experience
• Experience with RISC-V, or other processor architectures
• Mixed-signal verification experience
• Knowledge of machine learning/AI accelerator verification

Technical Excellence

• Deep analytical and problem-solving skills
• Ability to debug complex, multi-million gate designs
• Strong understanding of verification quality metrics

Leadership & Communication

• Excellent written and verbal communication skills
• Ability to mentor and develop engineering talent
• Cross-functional collaboration and influence
• Technical presentation skills

Personal Attributes

• Self-motivated with strong ownership mentality
• Detail-oriented with quality focus
• Adaptable to changing priorities
• Passion for innovation and continuous learning

Application Process

Interested candidates should submit:

• Current resume/CV
• Links to publications or GitHub projects (optional)

TDK Invensnese is an Equal Opportunity Employer

We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or veteran status.