STA Expert Engineer - ASIC Timing & Sign-off (R&D)

A leading technology company is seeking a STA expert engineer for its R&D team in the Paris area. The successful candidate will focus on timing constraints definition and analysis for integrated circuits. With a minimum of 5 years of experience in timing analysis tools, you'll work closely with design and flow teams to ensure timing closure for ASIC flows. This role requires a strong engineering background, expertise in TCL, and fluent English. Competitive compensation and opportunities for growth are offered.

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