RISC-V Debug, Trace & Profiling IP Architect

SiFive is seeking a hardware design engineer in La Ciotat, France, with extensive experience in designing advanced debug, trace, and profiling hardware for RISC-V architectures. The role involves collaborating with multiple teams to bring new hardware IP to market while ensuring high standards of quality and performance.

The ideal candidate will have 7+ years of industry experience and a strong background in RTL design, CPU architectures, and familiarity with debugging tools.