Precision Analog Data Converter Design

Job Responsibility

• Architect and define next-generation data converter solutions
• High-resolution and high‑speed ADCs (SAR, Sigma‑Delta (Discrete Time and Continuous Time), Time‑Interleaved)
• High-performance DACs (current steering, charge redistribution, segmented architectures)
• Translate system‑level requirements (SNR, SFDR, ENOB, bandwidth, power) into detailed architecture and sub‑block specifications
• Drive end‑to‑end design of data converters, including front‑end signal conditioning, references, and clocking
• High‑speed sampling circuits and precision analog core
• Calibration, linearity enhancement, and mismatch correction techniques
• Develop system‑level and behavioral models (MATLAB/Simulink, Verilog‑A/AMS) to validate architecture, noise shaping, and dynamic performance
• Lead detailed circuit design and analysis for critical blocks such as high‑speed comparators, opamps, DAC elements, reference buffers, and clocking circuits
• DAC mismatch and ADC linearity
• Perform deep analysis of performance metrics (SNR, SNDR, SFDR, INL/DNL, jitter sensitivity) and correlate with silicon results
• Drive silicon validation, debug, and performance optimization across PVT corners
• Serve as technical lead and interface with system teams, customers, and cross‑functional stakeholders
• Mentor junior designers and build technical depth in converter design methodologies across the organization
• Drive innovation and develop differentiated architectures, including patentable solutions

Your Profile

• MS in Electrical Engineering with 12+ years, or PhD with 10+ years of experience in ADC/DAC design
• Strong expertise across multiple data converter architectures: SAR, Sigma‑Delta (DT and CT), Time‑Interleaved ADCs, current steering and segmented DACs
• Proven track record in designing high‑performance converters
• Deep understanding of noise shaping, quantization noise, and distortion mechanisms
• Clocking and jitter impact on converter performance
• Calibration techniques (background/foreground, DEM, mismatch correction)
• Strong experience with high‑speed analog design challenges: bandwidth, settling, distortion, and parasitic effects
• Expertise in system‑level modeling and behavioral simulation (MATLAB/Simulink, Verilog‑A/AMS)
• Hands‑on experience with Cadence tools (Virtuoso, Spectre) and mixed‑signal simulation flows
• Proven ability to take converter designs from concept through silicon validation and production
• Demonstrated innovation capability with patents/publications in data converter design
• Strong communication skills with ability to influence cross‑functional teams and customers