Power and Solutions Engineer | SoC / ASIC / NoC / Power / Architecture

ASIC / NoC Power and Solutions Senior / Staff Engineer | SoC / ASIC / NoC / Power / Architecture

We are currently partnered with a global semiconductor technology company developing custom-built interconnect hardware IP, software tools, and advanced exploration and verification methodologies that enable SoC integration teams to achieve optimised Power, Performance and Area (PPA) characteristics.

Their technology sits at the backbone of modern SoC infrastructure, interconnecting major IP solutions while helping engineering teams maximise system performance and minimise integration cost. As part of their global Solutions Deployment organisation, they are looking to hire an ASIC / NoC Power and Solutions Senior / Staff Engineer to support the deployment and optimisation of NoC technology across a broad portfolio of SoCs spanning mobile, automotive, servers, IoT, connectivity, and other advanced applications, with a particular focus on power technologies.

Key responsibilities

• Collaborate with Architecture, Hardware, Software, Verification, Emulation, and other engineering teams to ensure NoC technology is deployed and used efficiently across SoC programmes
• Contribute to the definition of interconnect requirements, architecture, configuration, and power-related capabilities across multiple SoC designs
• Provide technical support for power-related issues and new NoC power solutions
• Analyse and resolve NoC power micro-architecture and power-unit integration challenges
• Support engineering teams in identifying, debugging, and resolving complex SoC power issues
• Participate in defining new and improved power architectures and NoC power units
• Take responsibility for the validation and technical deployment of new power technologies within the NoC environment
• Work closely with SoC architects and design teams to understand power requirements and translate them into effective interconnect solutions
• Contribute to optimisation of SoC Power, Performance and Area (PPA)
• Investigate power behaviour and system-level issues across simulation, emulation, and silicon bring-up environments

Key requirements

• Strong understanding of the overall SoC development lifecycle, including SoC architecture, RTL design, verification, performance analysis, DDR memory channels, physical implementation, silicon bring-up, and debug
• Good knowledge of system-level concepts including memory mapping, MMUs, Quality of Service (QoS), cache infrastructure, coherency, and security architectures
• Practical knowledge of low-power techniques in SoCs and experience identifying and resolving power-related issues
• Strong analytical and debugging skills across simulation, emulation, and/or silicon environments

Keywords

ASIC / SoC / NoC / Network-on-Chip / Power / Low Power / Power Architecture / Power Management / Power Optimisation / PPA / Solutions Engineer / Solutions Architect / Deployment Engineer / SoC Deployment / Interconnect / Hardware IP / ASIC Design / SoC Architecture / RTL / CPU / GPU / Cache / Memory Controller / DDR / Coherency / CHI / ACE / ACE-Lite / AXI / AHB / MMU / QoS / Security / Chiplets / High-Speed Protocols / Functional Safety / ASIL / ISO 26262 / Automotive SoC / Power Analysis / Power Debug / Simulation / Emulation / Silicon Debug / Post-Silicon / Verification / Semiconductor / Microelectronics / Hardware Architecture / Application Engineering / Technical Support / SoC Integration / PPA Optimisation / Global Engineering