Postdoc: FeFET Ternary IMC Architectures

The Post-Doctoral position at École Centrale de Lyon focuses on in-memory computing using FeFET-based ternary technology. You will design standard cell libraries, optimize ternary arithmetic units, and build system-level models for architecture simulators, enabling co-design of hardware and software for CNNs and DSP workloads.

Candidate should hold a PhD in microelectronics or related field, with strong HDL, EDA, and architecture experience and fluent English. French is welcome but not required.