Physical Design Contract

ASIC Verification | Physical Design Contracts

IC Resources is working with a client in Grenoble , looking for an engineer on a 12-month contract where you will be working onsite.

As a Senior Staff Physical Design Engineer, you will provide technical leadership for the physical implementation of next-generation, high-performance SoCs . This role focuses on advanced technology nodes, specifically 16nm FinFET and below, driving designs from RTL to final GDSII . You will be a technical pillar within the team, responsible for defining implementation strategies, mentoring junior engineers, and ensuring the delivery of market-leading PPA (Power, Performance, Area) targets.

Key responsibilities

• End-to-End Implementation: Lead the full RTL-to-GDSII physical design flow, including synthesis, floorplanning, placement, routing, CTS, and timing closure
• FinFET Strategy: Define and execute optimized implementation strategies tailored for FinFET challenges, such as advanced track patterns, secondary power grids, and complex DRC constraints
• Design Closure & Optimization: Perform Multi-Mode Multi-Corner (MMMC) timing closure and power optimization to meet aggressive PPA targets.
• Analysis & Verification: Conduct comprehensive power integrity analysis (IR drop/EM) and drive physical verification closure (DRC, LVS, ERC, Antenna) using industry-standard sign-off tools
• Cross-Functional Collaboration: Partner with RTL and DFT teams to ensure physically aware synthesis, congestion mitigation, and efficient scan-chain integration
• Technical Leadership: Act as a subject matter expert and mentor, interfacing with foundries and EDA vendors to resolve technology-specific challenges and driving EDA flow automation via Tcl, Python, or Perl

Candidate profile

• Education: Master’s degree in Electrical Engineering or a related technical field
• Professional Experience: 10+ years of expertise in full-custom layout for memory and/or analog/mixed-signal IPs
• Technical Mastery: Deep knowledge of physical constraints, including matching, EM, IR drop, and antenna rules
• Tool Proficiency: Expert-level command of layout and sign-off tools (e.g., Virtuoso, Calibre); proficiency in CAD scripting is highly valued
• Advanced Expertise (Pluses): Experience with emerging memories (MRAM, RRAM), in-memory computing layout, and advanced CMOS nodes
• Soft Skills: A self-directed and organized professional with excellent communication skills, capable of engaging effectively with internal stakeholders and external partners. Fluency in English is required; knowledge of French or Dutch is a bonus