PhD Position on the design of a self-triggered readout architecture for ultra-fast sampling

Overview

In modern high-energy physics experiments, the extremely precise measurement of particle arrival times (resolution on the order of tens of picoseconds) has become an essential requirement to cope with very high luminosity and event pile-up. The ultra-fast analog signal sampling technique has established itself as one of the highest-performing methods, as illustrated by the success of the SAMPIC family of circuits. Recently, the SPIDER ASIC was developed for the LHCb experiment (at the CERN LHC), proposing a multi-bank digitization architecture that is highly efficient in terms of dead time. Like SAMPIC, it is self-triggered but optimized for a signal arrival that is quasi-synchronous with the clock. However, for most applications outside of large collider detectors, circuits must be able to operate with random signals. This means that a new circuit should be capable of continuously sampling the signal like SAMPIC, offering multi-bank switching capability to optimize dead time like SPIDER, and triggering digitization autonomously without waiting for a global external validation signal, just like its two predecessors. This PhD project is at the heart of a joint Research and Technology (R&T) program between the LPCA (Clermont-Ferrand), IJCLab, and IRFU (Saclay). The objective is to design the architecture of this next generation of fast samplers.

Responsibilities / Project Axes

• Axis 1: Modeling and System Architecture Work - Before designing the transistors at the physical level, specification and architectural definition work is essential to validate the system\'s behavior when faced with high, random data fluxes. The PhD student will model the complete architecture of the circuit (sampling cell matrix/matrices, time memory management, trigger logic) using a behavioral description language (SystemVerilog). This step will help support and refine the architectural choices and verify the circuit\'s functionality against various scenarios.
• Axis 2: Design and Optimization of the Analog Block and Embedded Digital Logic - The input stage must be redesigned to extend the self-triggering and buffering functions to continuous sampling. The addressing of the Switched-Capacitors Arrays inherited from SPIDER will need to be adapted to allow continuous writing and sampling switching driven by the local trigger. This step will require developments on the analog side as well as developing the logic (RTL) to manage the allocation of the analog memory blocks.
• Axis 3: Integrated Digital Correction - The digitization of the samples is affected by systematic non-uniformities, which must be corrected after acquisition. The goal of this 3rd axis is to explore the feasibility of an at least partial correction embedded directly on the chip (pedestal subtraction) and, if applicable, to develop its implementation (including the calibration of coefficients through dedicated acquisitions).

Location

The activity of the LPCA (Clermont Auvergne Physics Laboratory), located on the Cézeaux campus in Aubière, is dedicated to Particle and Nuclear Physics, Cosmology, and Theoretical Physics, as well as applications in the fields of Health and Environment. This laboratory includes technical support and development services and platforms for its scientific activities and those conducted with its partners. The project will be carried out within the LPCA\'s MiCA (Clermont Auvergne Microelectronics) platform. The intern will be supervised by a research engineer specializing in mixed-signal design, and will interact with digital design experts. This topic is of strong interest to the MiCA platform, offering an open field of applications and demonstrating both academic and industrial relevance.

Required Profile

You hold a Master\'s degree or an Engineering degree (equivalent to 5 years of higher education), with a specialization in microelectronics/integrated circuit design and verification. You have a solid foundation in integrated circuit architecture as well as analog and digital design, and you are proficient in at least one HDL language. You possess a strong sense of investigation and methodology. You demonstrate curiosity, autonomy, and the ability to see a project through to completion.

Contacts

To apply, please send a CV and a cover letter to:

Hervé Chanal: