Mixed-Signal IC Design Engineer: RTL to Tape-Out

Arago is seeking a senior digital RTL designer to design, verify, and deliver high-performance digital subsystems inside mixed-signal ICs. You will own the flow from RTL to physical implementation and tape-out, interfacing with analog teams to optimize cross-domain performance.

The role emphasizes Verilog/SystemVerilog expertise, hands-on EDA toolchain use, and collaboration across hardware disciplines. English is required; French is a plus, and relocation support is provided.