MEMS - Digital Verification - SR

Your Role

Position is aimed at a Digital Verification Engineer with experience in digital verification of ASIC. The candidate will join the digital verification team of the MEMS Group and will see all ASIC verification process from specification definition up to final product industrialization.

Responsibilities include definition and development of verification testbench, development of verification components, development of DSP models and digital control logic, test‑case development for simulation, debugging failures, and creating simulation cases for various scenarios.

Location: Toulouse (France). Senior profile required.

Your Skills & Experiences

• Preferred seniority: 3 to 5 years of experience.
• Background in digital verification testbench (UVM and SystemVerilog), with experience in digital simulator tools.
• UVM, SystemVerilog assertion, coverage, self‑checking capabilities, testbench automation, bug analysis and reporting.
• Basic knowledge of Python scripts, TCL scripts, and version control system.
• Knowledge of formal verification and communication protocols (I2C, SPI, I3C) is a plus.
• Soft skills: good communication, fluency in English, teamwork and collaboration across the MEMS Group Design team.

Equal Employment Opportunity Statement

At ST, we endeavor to foster a diverse and inclusive workplace, and we do not tolerate discrimination. We aim to recruit and retain a diverse workforce that reflects the societies around us, strive for equity in career development, career opportunities, and equal remuneration. We encourage candidates who may not meet every single requirement to apply, as we appreciate diverse perspectives and provide opportunities for growth and learning. Diversity, equity, and inclusion (DEI) is woven into our company culture.