Lead Debug & Profiling Architect for RISC-V IP

SiFive, Inc. is looking for a Lead Debug/Trace/Profiling Design Engineer in La Ciotat, France. The candidate will be responsible for designing innovative debug hardware utilizing the RISC-V architecture.

This role involves collaborating with various teams to ensure optimal performance and quality in hardware design. A minimum of 7 years of relevant experience and an MS/PhD in a technical field is required.

Join SiFive and play a crucial role in revolutionizing the future of compute.