III/V Process Integration, Layout and Characterization Engineer

As a member of the R&D, the III/V Process Integration, Lay-out and Characterization Engineer will play a key role in the evaluation, selection and optimization of advanced technologies. The selected candidate will work directly with external III-V foundry partners and will also coordinate closely with internal departments (design, industrialization, packaging, testing).

The candidate will own layout definition aligned with process integration flows, drive interactions with foundries, and contribute to device fabrication, testing, and characterization.

Responsibilities

Process Integration & Layout

§ Define and optimize process integration flows for photonic devices

§ Translate process flows into robust layout designs (mask layouts)

§ Ensure layout compliance with foundry design rules (DRC, LVS when applicable)

§ Collaborate with design teams to ensure feasibility and performance

Foundry Interface

§ Act as primary technical contact with external foundries (fabless model)

§ Manage tape-outs, process reviews, and fabrication iterations

§ Support debugging and yield improvement with foundry partners

Fabrication & Characterization

§ Contribute to device fabrication in partner or internal facilities when needed

§ Perform electro-optical characterization of devices

§ Analyze results and close the loop with design and process improvements

Cross-Functional Collaboration

§ Work closely with R&D and industrialization team members across Design, Process development, Packaging and Testing

§ Support problem-solving across the full product lifecycle

Qualifications

§ Master's degree or PhD in Materials Science, Semiconductor Physics, or a related field

§ Minimum 5 years of experience in process integration (PIC, semiconductor, or MEMS) (or PhD + 2 years)

• Strong background in process integration (semiconductor or photonics)
• Hands-on experience in layout design tied to process flow
• Knowledge/experience with:
• InP / AsGa laser process flows
• LNO (Lithium Niobate on Insulator)
• MTP / photonic integration platforms
• Familiarity with:
• PDKs and foundry design constraints
• Device physics (photonic / optoelectronic devices)
• Experience in device characterization (optical + electrical)
• Ability to analyze performance metrics and link back to process/design
• Practical approach to debugging and iteration
• Strong problem-solving mindset
• Comfortable working in a fabless, multi-partner environment
• Excellent team player within an R&D setting
• Ability to operate across disciplines

Desirable Qualifications (Nice to Have):

• Experience working directly with external foundries or MPW runs
• Knowledge of packaging constraints in photonics
• Familiarity with layout tools (e.g., KLayout, Cadence, L-Edit, etc.)

This position will require some regular travels abroad (Europe, US, Asia) (1 / quarter).

Why Join Us

• Join an innovative company at the forefront of semiconductor photonic technology
• Work in a dynamic and collaborative environment
• Enjoy opportunities for career advancement and personal development
• Competitive salary and benefits package