FPGA Prototyping Engineer

Prototyping Design Engineer – Snap Inc. (Specs Inc.)

Responsibilities

• Port SoC and subsystem RTL onto FPGA, HAPS, and ZeBu platforms while keeping the prototyping code as close as possible to ASIC RTL and carefully managing target‑specific conditionals.
• Rework RTL, wrappers, and platform‑specific logic for prototyping targets, including HAPS/ZeBu‑specific interface PHY changes and controller‑presence handling to support common software flows across SoC, ZeBu, HAPS, and FPGA platforms.
• Debug complex hardware issues across HAPS, ZeBu, and FPGA targets, including memory‑model integration, reset and clock sequencing, controller/PHY interaction, timing issues, waveform analysis, and timing‑report review.
• Partner with SoC, verification, infrastructure, and external vendors to root‑cause issues and accelerate pre‑silicon readiness.
• Integrate prototyping platforms into CI/CD flows and improve build reliability, automated regressions, artifact traceability, and shared platform infrastructure.

Knowledge, Skills & Abilities

• Strong understanding of SoC RTL integration and the tradeoffs required to map large designs onto prototyping and emulation platforms.
• Hands‑on experience with FPGA prototyping and hardware emulation platforms such as HAPS, ZeBu, or similar Cadence/Siemens/Synopsys environments.
• Experience with static timing analysis for XILINX/Intel FPGA platforms.
• Familiarity with ARM Cortex‑M/R/A architectures, SoC peripherals, and system interfaces such as LPDDR/DFI, eMMC, PCIe, JTAG/SWD, UART, SPI, I2C/I3C, GPIO, and QSPI flash.
• Experience debugging clocks, resets, timing issues, waveforms, platform bring‑up problems, and embedded software crashes or asserts across multiple pre‑silicon targets.
• Ability to work from RTL, hardware schematics, datasheets, and timing reports, and to communicate platform limitations and integration constraints clearly across hardware and software teams.
• Strong problem‑solving, communication, teamwork, and prioritization skills in a fast‑paced cross‑functional environment.

Minimum Qualifications

• Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 5+ years of experience in SoC prototyping, FPGA/emulation bring‑up or pre‑silicon validation.
• Experience with RTL integration, FPGA prototyping, hardware emulation, or pre‑silicon validation.

Preferred Qualifications

• Experience with Siemens, Synopsys or Cadence emulation platforms.
• Experience running embedded software, diagnostics, or RTOS‑based applications on FPGA or emulator platforms.
• Experience building or maintaining CI/CD pipelines for hardware prototyping such as GitLab or TeamCity.
• Experience working closely with system software teams and validation enablement.

EEO Statement

Snap Inc. is a proud equal‑opportunity employer and is committed to providing employment opportunities regardless of race, religious creed, color, national origin, ancestry, physical disability, mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, pregnancy, childbirth and breastfeeding, age, sexual orientation, military or veteran status, or any other protected classification in accordance with applicable federal, state, and local laws. EOE, including disability/vets.

If you have a disability or special need that requires accommodation, please let us know.

Benefits

Benefits include paid parental leave, comprehensive medical coverage, emotional and mental health support programs, and compensation packages that allow employees to share in long‑term success.