Digital Verification Engineer

A well-established European semiconductor company expanding it's team, is looking for a Senior Digital Verification Engineer to strengthen the team and offer a clear path to leadership.

Key responsibilities

• Define verification strategies and detailed plans based on product specifications
• Build and maintain advanced UVM-based verification environments
• Develop SystemVerilog testbenches and coverage-driven test strategies for configurable IP
• Execute functional, performance, and power verification activities
• Analyse potential reliability weaknesses and recommend safety improvements
• Support design teams throughout development and validation cycles

Candidate Profile

The company is looking for an verification professional with an engineering degree (Master’s or equivalent) and at least five years of relevant industry experience.

Technical skills

• Bachelors or Masters in Electronic Engineer or a related field plus 5 years of industry experience
• Strong hands-on experience with UVM in complex verification environments
• Solid understanding of functional coverage and constrained-random verification
• Practical RTL experience using Verilog/SystemVerilog
• Experience with Formal Verification is nice to have
• Knowledge of low-power verification concepts and UPF standards is nice to have