Digital Verification Engineer

** All candidates must have EU nationality**

I'm looking for an experienced Digital Verification Engineer to join a team working on advanced SoC and ASIC designs.

You’ll contribute to the verification of complex digital systems, working closely with design and mixed-signal engineers to ensure high-quality silicon delivery.

Key responsibilities

• Develop and execute UVM-based verification environments and testbenches
• Define and implement verification plans for complex ASIC subsystems
• Work across digital, mixed-signal, and validation teams
• Support verification IP development and system-level simulations
• Contribute to debug and coverage closure activities

About you

• MSc or PhD in Electrical Engineering or similar field
• Strong experience with SystemVerilog/UVM
• Good understanding of ASIC design flow and verification methodologies
• Scripting experience (Python, TCL, Makefiles)
• Experience with interfaces like PCIe, Ethernet, DDR, or CPUs is a plus
• Familiar with simulation or formal tools (Cadence/Synopsys advantageous)

This role is based in Paris, Caen, or Grenoble with flexible remote working options.

For more information on this role or others, please contact Jordan Browne at IC Resources.