DFT Engineer for SoC/ASIC – Design for Testability

NanoXplore SAS is seeking a DfT Engineer to own DfT insertion from specification to silicon bring-up in advanced nodes (28nm to 7nm and beyond). You will define strategies with SoC architects and guide the implementation with design teams, ensuring validation before tape-out and support after tape-out.

You will work in a multidisciplinary team with digital design, layout, and engineering, engaging with international customers in aeronautics and defense, and upholding ISO-9001 quality procedures.