DFT (Design For Testability) Engineer (F/M)

NanoXplore is a French fabless semiconductor company founded in 2010. Since 2014, in partnership with ESA, CNES, and the European Commission, we have been delivering innovative FPGA and SoC FPGA technology solutions, with the additional capability to develop ASICs and dedicated solutions.

In 2024, NanoXplore acquired the ASIC activities of Dolphin Design, strengthening its strategy to offer a complete portfolio of semiconductor solutions. The NX Design Services team brings over 20 years of expertise in custom ASIC development, with a strong track record in high-reliability and low-power circuits.

Due to our rapid expansion, we are looking for a DFT (Design For Testability) Engineer.

YOUR MISSION:

DfT Insertion & Ownership

• Own the definition, implementation, and management of DfT insertion, from specification through silicon bring-up.
• Define DfT strategies in collaboration with SoC architects and drive their implementation with design teams, ensuring pre-tape-out validation and post tape-out support.
• Work on advanced technology nodes, from 28nm to 7nm and beyond.

Design Flows & Technical Leadership

• Maintain and continuously improve DfT design flows, including associated documentation.
• As DfT technical reference, contribute to pre- and post-sales activities, estimations, planning, and risk analysis.
• Grow, as you wish, toward increased technical responsibilities, project management, or team leadership.

Collaboration & Cross-functional Environment

• Work within a multidisciplinary team recognised for its expertise, in close collaboration with digital design, layout, and engineering teams.
• Engage in technical exchanges with major international customers in the aeronautics and defense sectors.
• Thrive in a demanding multicultural environment, supported by management that is committed to your professional growth.
• Ensure compliance with ISO-9001 quality procedures across all project phases.

YOUR STRENGHTS:

• Strong team spirit and communication skills to work effectively with a cross-functional and multicultural environment.
• Commitment to quality and adherence to ISO-9001 procedures throughout all project phases.
• Initiative and ability to champion technical proposals in a fast-growth context.
• Intellectual curiosity and a genuine interest in new technologies across ASIC, FPGA, and SoC domains.
• Good command of written and spoken English, essential for interactions with international customers and partners.

SKILLS & EXPERIENCE:

Education

• Master’s degree or equivalent in Microelectronics, with a first experience in DfT insertion on an IP or ASIC.

Experience

• Strong command of DfT concepts: Memory BIST, scan, boundary scan, Logic BIST, IJTAG protocol.
• Experience with at least one DfT insertion tool: Modus (Cadence), Tessent (Siemens/Mentor), or TestMax (Synopsys).

Technical Skills

• Proficiency in Cadence EDA tools: Genus, Tempus, LEC, XCelium.
• Proficiency in Synopsys EDA tools: Design Compiler, PrimeTime, Formality, VCS.
• Proficiency in Siemens/Mentor EDA tools: Tessent, Questa.
• Knowledge of advanced technology nodes (28nm to 7nm and beyond) and associated constraints (high reliability, low power).
• Good command of HDL languages (VHDL, Verilog, SystemVerilog) and embedded communication protocols (AXI, AHB, APB).
• Proficiency in versioning tools (Git, SVN) and technical documentation practices.

WHAT WE OFFER :

A position preferably based in Meylan (38); possible workplace based in Jacou or Sèvres for high-value candidate.

• Contract type: Full Time & Permanent (CDI)
• Package: salary according to profile + internal benefits