Cutting-Edge Cache Coherence Architect for SoC/NoC

Arteris is seeking a Cache Coherency Architect to define and optimize cache coherency solutions within our NoC IP portfolio. You will develop cutting-edge cache coherent interconnect IP for seamless integration with other NoC IP and system IP, enabling efficient communication across multiple cores and functional units.

You will collaborate with hardware designers, verification engineers, software developers, and stakeholders to deliver high-performance, power-efficient IP.