ASIC / NoC Verification & Solutions Engineer- Qualcomm - Guyancourt, France

Company:Qualcomm France S.

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Job Area:Engineering Group, Engineering Group > ASICS Engineering

General Summary:Qualcomm France-QITC's mission is to develop and deploy highly configurable custom-built interconnect hardware IPs (No

Cs), software tools, and exploration and verification methodologies. This enables So

C integration teams to quickly assemble and verify So

Cs with the desired Power Performance Area (PPA) characteristics. QITC technology embraces the complete So

C infrastructure to provide increased So

C performance at minimal cost for integration. Our work is at the backbone of the So

C, interconnecting all major IP solutions.

Qualcomm Interconnect Technology Center (QITC) has been breaking ground in interconnect design for 15 years and continues to innovate and deliver technology in line with the latest evolutions in So

C design.

QITC No

C solution tools include a full suite of automated interconnect design and verification tools that improve user productivity. In particular, No

C verification tools include state-of-the-art Verification IPs, UVM benches, and scoreboards, used to check No

C assembly and No

C-level features. The UVM bench is automatically generated by the software, allowing it to map to all No

C varying topologies and features.

You will join the Solutions deployment team with the mission of deploying and supporting the QITC No

C Verification technology across all the So

Cs in Qualcomm's portfolio (Mobile, Automotive, Servers, Io

T, Connectivity, etc.). The job involves providing verification support, including analyzing complex scenarios of No

C simulations, understanding the behavior of verification components, benches, and their associated automation tools in compliance with current ASIC verification standards like UVM.

This is a challenging position with a lot of inter-team communication. You will be working on the most innovative technologies, surrounded by experts and users of our technology from various teams (So

C Architecture, HW and SW Design, Verification, Debug, Post Silicon) worldwide.

Responsibilities:In your role, you will:Collaborate regularly with highly skilled experts across different teams (Architecture, Hardware, Software, Verification, Emulation, etc.) to ensure our Verification technology is used efficiently in Qualcomm So

Cs.

Contribute to the definition and enhancement of the No

C Verification environment and its configuration in the various So

Cs.

Be responsible for the technical support of new No

C verification solutions.

Help resolve No

C testbench or DUT simulation issues.

Participate in defining new Verification solutions and improvements for our technology.

Develop in-depth technical material and organize training sessions for different teams worldwide.

The working environment will consist of: Verilog, System

Verilog, UVM, Python, Linux, Shell, Git, Synopsys, or Mentor Graphics verification tools.

Skills/Experience:Experience in using or designing UVM components, benches, or VIPs.

Strong analytical skills for debugging in simulation, emulation, or silicon bring-up environments.

Understanding of interconnect protocols like AHB/AXI/ACE/ACE-Lite/CHI/No

C concepts.

Understanding of overall So

C development flow: So

C architecture, RTL design and verification, So

C performance and DDR memory channel, physical implementation, silicon debug.

Good knowledge of system-level features such as memory-mapping, MMUs, Quality of Service, cache infrastructure, security schemes, etc.

Proficiency in Python & Perl scripting.

Ability to quickly react and adapt to changes.

Excellent communication skills.

Minimum Qualifications:Master’s degree in Microelectronics, Computer Science, or a related field.

Standard So

C knowledge: Multimedia IPs, GPU, multi-core CPU architecture, Processors, Caches, memory controllers, interconnects, and related design, integration, and verification challenges.5 years of solid experience in verification and/or design for So

C/ASIC engineering development cycles.

Preferred Qualifications:Experience in using or designing UVM components, benches, or VIPs.

What's on Offer:Friendly and collaborative working environment.

Salary, stock, and performance-related bonus.

Maternity/Paternity Leave.

Employee stock purchase scheme.

Matching pension scheme.

Education Assistance.

Life, Medical, Income, and Travel Insurance.

Keywords:So

C, ASIC, Verification, Simulation debug, Interconnect, Cache, CPU, GPU, Coherency, Debug

Minimum Qualifications:Bachelor's degree in Science, Engineering, or related field.*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail or call Qualcomm's toll-free number found here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

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