ASIC / NoC SoC deployment architect - Qualcomm - Guyancourt, France

Company:Qualcomm France S.

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Job Area:Engineering Group, Engineering Group > ASICS Engineering

General Summary:The QITC mission is to develop and deploy custom-built interconnect hardware IPs, software tools, and exploration and verification methodologies so that So

C integration teams can quickly assemble So

Cs with the desired Power Performance Area (PPA) characteristics.

To this end, QITC technology embraces the complete So

C infrastructure to provide increased So

C performance at minimal cost for integration. Our work is at the backbone of the So

C, interconnecting all major IP solutions.

You will join the solutions deployment team with the mission of deploying and supporting the QITC No

C technology across all the So

Cs of Qualcomm portfolio (Mobile, Automotive, Servers, Io

T, Connectivity, etc..).

This is a challenging position, working on most innovative technologies, surrounded by experts but also by users of our technology all over the world and from various teams (So

C Architecture, HW and SW Design, Verification, Debug, Post Silicon).

Responsibilities

In your role, you will:Collaborate regularly with highly skilled experts across different teams (Architecture, Hardware, software, verification, emulation, ...) to ensure our technology is used efficiently in Qualcomm So

Cs

Contribute to the definition of interconnect requirements and configuration in the various So

Cs

Be responsible for the technical support of new QITC solutions

Help resolving No

C micro-architecture and No

C integration issues

Participate in defining new solutions and improvements for our technology

Develop in-depth technical material and organize trainings for different teams worldwide

Skills/Experience

Strong understanding of overall So

C development flow: So

C architecture, RTL design and verification, So

C performance and DDR memory channel, physical implementation, silicon debug.

Good knowledge in system level features such as memory-mapping, MMUs, Quality of service, cache infrastructure, security schemes, etc..

Strong analytical skills for debug in simulation, emulation or silicon bring-up environments.

Understand of interconnect protocols like AHB/AXI/ACE/ACE-Lite/CHI/No

C concepts.

Python & Perl scripting

Ability to quickly react and adapt to changes.

Excellent communication skills.

Minimum Qualifications

Master’s degree in Microelectronics, Computer Science, or related field.

Preferably 5-10 years of solid experience in design, architecture and/or application engineering in So

C/ASIC development cycle.

Standard So

C knowledge: Multimedia Ips, GPU, multi-core CPU architecture, Processors, Caches, memory controller, interconnects, ... and related design, integration and verification challenges

Preferred Qualifications

One or multiple qualifications in the below list would be a great advantage:So

• Coherency protocols Keywords So

C, ASIC, Deployment, Solutions Architect, Interconnect, Cache, CPU, GPU, Coherency, debug, verification

What's on Offer:Friendly and collaborative working environment.

Salary, stock, and performance-related bonus.

Maternity/Paternity Leave.

Employee stock purchase scheme.

Matching pension scheme.

Education Assistance.

Life, Medical, Income, and Travel Insurance.

Keywords:So

C, ASIC, Verification, Simulation debug, Interconnect, Cache, CPU, GPU, Coherency, Debug

Minimum Qualifications:Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

ORMaster's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.

ORPh

D in Science, Engineering, or related field.*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

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